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LAS VEGAS — AMD aggressively expanded its artificial intelligence infrastructure portfolio at CES 2026, unveiling a massive liquid-cooled server rack, next-generation silicon architectures, and a new desktop platform designed to run large language models locally. In a keynote focused heavily on scaling AI from the data center to the edge, CEO Dr. Lisa Su introduced the "Helios" AI rack and the MI455 GPU, positioning the company to compete directly for the high-performance computing contracts powering the world's largest AI models.
Key Developments
- Helios AI Rack: A 7,000-pound, liquid-cooled OCP-standard rack delivering 2.9 exaflops of performance.
- MI455 GPU: The latest Instinct chip featuring 320 billion transistors and 432GB of HBM4 memory.
- Venice CPU: A 2nm EPYC processor utilizing Zen 6 architecture with up to 256 cores.
- Ryzen AI Halo: A dedicated AI development desktop capable of running 200-billion parameter models locally.
- Robotics Expansion: Preview of "Gene 1," a tactile-sensing humanoid robot entering production in late 2026.
Infrastructure Scale: The Helios Rack and MI455
The centerpiece of AMD’s presentation was Helios, a "double-wide" AI rack developed in collaboration with Meta based on Open Compute Project (OCP) standards. Designed to maximize density and serviceability, the system represents a significant shift toward integrated data center solutions.
According to Dr. Su, the rack weighs nearly 7,000 pounds and utilizes liquid cooling to manage the immense thermal output of next-generation silicon. The system creates a dense compute fabric, offering an aggregate scale-out bandwidth of 43 terabytes per second.
"Helios is a monster of a rack... it is actually more than two compact cars. We chose this design so that we could optimize serviceability, manufacturability, and reliability for next-generation AI data centers." — Dr. Lisa Su, AMD CEO
Powering this infrastructure is the new MI455 Instinct GPU. Built using a combination of 2nm and 3nm process technologies, the chip represents a 70% increase in transistor count compared to its predecessor, the MI355. AMD emphasized the memory architecture, equipping the GPU with 432GB of ultra-fast HBM4 memory to alleviate the bottlenecks often faced during the training of massive foundation models.
The Venice Architecture: Zen 6 Arrives
AMD also provided the first detailed look at its next-generation CPU, code-named "Venice." Built on a 2nm process, Venice introduces the Zen 6 core architecture, pushing core counts to 256 per socket.
The processor is explicitly engineered to act as a "feeder" for AI workloads. AMD has doubled the memory and GPU bandwidth from the previous generation to ensure that the MI455 GPUs remain fed with data at full speed. This co-engineering strategy—optimizing the CPU, GPU, and Pensando networking chips to work in concert—aims to lower the total cost of ownership for hyperscale operators.
Specs at Scale
When fully populated, a single Helios rack contains:
- More than 18,000 CDNA 5 GPU compute units
- Over 4,600 Zen 6 CPU cores
- 31 terabytes of HBM4 memory
- Up to 2.9 exaflops of theoretical performance
Consumer and Edge AI: Ryzen AI Halo
Moving beyond the data center, AMD announced the Ryzen AI Halo, a reference platform targeting developers and power users who need to run AI workloads without cloud dependency. Launching in the second quarter of 2026, the device is marketed as the "world's smallest AI development system."
The Halo unit features 128GB of high-speed unified memory shared across the CPU, GPU, and NPU. This unified architecture allows the compact device to run models with up to 200 billion parameters locally. AMD positions this as a critical tool for developers building agents and applications that require data privacy or offline functionality.
Concurrently, the company launched the Ryzen AI 400 series for mobile computing. Shipping later this month, these processors combine Zen 5 CPU cores with RDNA 3.5 graphics and XDNA 2 NPUs, delivering up to 60 TOPS (trillions of operations per second) of AI compute performance. The chips are slated for integration into more than 120 laptop models throughout the year.
Robotics and Future Applications
The keynote concluded with a forward-looking demonstration of "Gene 1," a humanoid robot featuring a distributed tactile skin. Unlike traditional robots that rely primarily on vision, Gene 1 utilizes pressure and contact as primary sources of intelligence, allowing for safer human-robot collaboration in industrial and healthcare settings.
"For us, acceptability means beauty, grace, and safety... A distributed tactile skin across the robot body allows Gene 1 to feel pressure, contact, and intention, making touch a primary source of intelligence."
The robot is powered by AMD compute platforms and is scheduled for commercial manufacturing in the second half of 2026, with pilot programs already planned with leading steel manufacturers.
With the immediate release of the Ryzen AI 400 series and the upcoming rollout of the Venice and Helios infrastructure, AMD is executing a strategy to provide the hardware foundation for the next phase of the AI economy, spanning from handheld devices to exascale data centers.
